A novel simulation methodology for full chip-package thermo-mechanical reliability investigations

A methodology for simulating the accurate 3D structural details of a non-planarized technology chips is presented. FEM is a powerful tool used for electrical, thermal and mechanical analysis in the microelectronics industry. Manual geometry and finite element mesh generation of a 3D non-planar chip topology is extremely tedious and time consuming. Therefore, a new method, which is automatic or semi-automatic, is required to drastically reduce the pre-processing effort required for finite element simulations. Our proposed approach uses a virtual semiconductor fabrication technique to create geometry and finite element mesh on complex chip topology features. A microscopic power metal stack of a power IC was simulated to demonstrate this new simulation methodology and the results are presented. These numerical simulations, which included the non-linear behavior in the matrix, show that the detailed information of the large stress and strain gradients in the micro-fields can be obtained.