Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
547180 | Microelectronics Reliability | 2012 | 11 Pages |
Abstract
In this review article, the scaling challenges of planar non-volatile memory, especially the flash-types including both floating gate-based and charge-trap-based devices are firstly discussed. The promising prospects brought by 3-Dimensional (3-D) nano-wire-based cells have been presented along with various device demonstrations and discussions on vertical nano-wire platform. The memory devices with highly scaled single-crystal Si nanowire (SiNW) channel and a gate-all-around (GAA) structure achieve superior program/erase (P/E) speed, cycling and high-temperature retention characteristics as compared to the planar one and are considered as promising candidate for future ultra-high non-volatile flash memory application.
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Authors
HongYu Yu, Yuan Sun, Navab Singh, Guo-Qiang Lo, Dim-Lee Kwong,