Off-state drain breakdown mechanisms of VDMOS with anti-JFET implantation

Efficiency, reliability, and cost are the important design considerations of a vertical double diffused MOSFET (VDMOS) because of its high-voltage applications in consumer electronics. To minimize the cost, the devices were normally fabricated on an epitaxial layer which was grown on a highly-doped substrate. Meanwhile, it was proposed that the efficiency of a VDMOS can be enhanced by conducting an anti-JFET implant to reduce the “ON” resistance of the transistor. This paper reports the effects of anti-JFET implant on the reliability and the blocking capability of the VDMOS. Experimental results show that the anti-JFET implant can reduce the ON resistance by suppressing the channel depletion due to the parasitic JFET and enhance the breakdown voltage by moving the high-field region to the surface channel region. However, it deteriorates the device reliability greatly because the oxide quality was deteriorated and the hot holes generated in the surface high-field region could be easily injected into the gate oxide and hence caused larger subthreshold conduction and drain breakdown at lower voltage.

► We investigate the reliability of VDMOS on low cost epi-layer with anti-JFET implant. ► The reliability of the use of anti-JFET implant relies on proper process control. ► The BV degradation is due to charge trapping in deteriorated gate oxide. ► The BV degradation is also due to charge trapping in deep P-base region. ► There is design trade-off between use of low cost epi-layer and anti-JFET implant.