Article ID Journal Published Year Pages File Type
547383 Microelectronics Reliability 2011 5 Pages PDF
Abstract

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO2-dominated high-k gate dielectrics is like mobile defect; while that with SiO2-dominated ones is similar to the near-interface/border trap.

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