Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process

A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to protect the ultra-thin gate oxide effectively in nanoscaled integrated circuits. This device is designed and verified in a 65 nm CMOS process. With increased substrate resistance and pumped triggering current provided by power bus controlled PMOS, this structure features a significantly reduced trigger voltage of 2.8 V and an enhanced uniform conduction of multi-fingers. The failure current can be improved by 23.5% compared with traditional GGNMOS.

► Substrate-Engineered Gate-Grounded NMOS structures are designed in 65 nm process. ► Substrate-triggering technique and dynamic substrate resistance technique are used. ► It features a low trigger voltage of 2.8 V. ► Failure current can be improved by 23.5% due to uniform conduction of multi-finger.