A high o/p resistance, wide swing and perfect current matching charge pump having switching circuit for PLL

The charge pump (CP) circuit is one of the main building block in a phase-locked loop (PLL) based frequency synthesizers. In conventional CMOS charge pump circuits, there are some non-ideal effects such as clock feed through, current mismatch and charge sharing which result in a phase offset in phase-locked loop circuits.This paper presents a new charge pump circuit in 0.18μm CMOS technology, which greatly reduces the mismatch of current between two branches of the cascode current mirror. By using this proposed architecture, the mismatching between the UP/DN current of the CP can be achieved with less than 0.065% from post-layout simulation. As a result the spur and also the overall phase noise of the PLL are reduced. The charge pump output voltage range is 0.40–1.25 V. Additionally, the proposed circuit has wide output voltage swing and high output resistance, which ensures its good performance under very low power supply. Further, this CP circuit is incorporated with a new switching circuit to eliminate the clock feed through and charge injection error.