| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 547462 | Microelectronics Journal | 2013 | 5 Pages |
A split compensation for inverter-based self-biased two-stage amplifier is presented in this paper with detailed quantitative analysis. The conventional miller capacitor is split into two parts to accomplish frequency compensation. With the split compensation, the non-dominant poles and their corresponding Q-values are independent on the parasitic parameter, moreover, this compensation together with inverter-based input stage and the self biased technique improves the performance such as DC gain, gain-bandwidth product, stability and sensitivity. The proposed amplifier has been implemented in a SMIC 0.13 μm CMOS process and the chip area is 0.10×0.14 mm2. It achieves 10.2-MHz gain-bandwidth product when driving a 20-pF capacitive load dissipating 97.2 μW power at 1.2 V supply, which shows an improvement in IFOMS and IFOML performance.
