A 2×VDD output buffer with PVT detector for slew rate compensation

A novel PVT (process, voltage, temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, supply voltage, and temperature (PVT) is detected, respectively. Based on the detected PVT corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output can be adjusted as well. The proposed design is implemented using a typical 90 nm CMOS process to justify the slew rate performance. By the on-silicon measurements, the slew rate of output signal is compensated over 26%, the maximum slew rate is 1.65 (V/ns), the maximum data rate is 330 MHz given 1.2/0.9 V supply voltage with a 20 pF load, the core area of the proposed design is 0.056×0.406 mm2, and the power consumption is 2.2 mW at 330 MHz data rate.