Experimental and numerical analysis of current flow homogeneity in low voltage SOI multi-finger gg-NMOS and NPN ESD protection devices

Triggering uniformity and current sharing under TLP stress is investigated in low voltage multi-finger gg-NMOS and NPN ESD protection devices fabricated in smart-power SOI technology. Inhomogeneous current distribution over the fingers and within a single finger is detected by the backside transient interferometric mapping (TIM) technique. 2D TCAD device simulations of the multi-finger devices are used to explain the experimental TIM results. Changes in differential resistance in the pulsed IV characteristics of the NPN ESD protection devices are also explained by TIM experiments.