Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates

In order to have a high level of confidence in system testing, more accurate fault models are needed. An accurate fault model cannot be attained unless all faults in the transistor-level (low level) are considered. However, these transistor-level faults must be mapped onto gate-level (higher level) so that the efficiency of fault simulation, fault emulation and test pattern generation at the gate-level is not sacrificed. This paper covers the static and dynamic single physical failures at transistor-level for static CMOS primitive gates and shows their effects in the output behavior in terms of gate-level faults. A specific fault pattern is proposed and a general formula to calculate the total number of static faults is concluded from these patterns for each type of gate regardless of its number of inputs. The dynamic nature of the physical faults included in the static fault list is evaluated and their cumulative effect on the timing at the circuit output is examined. A general formula for calculating propagation delay at the output due to resistive shorts and opens is derived and a delay fault pattern with variable defect resistance is provided.