Design of a high-speed sample-and-hold circuit using a substrate-biasing-effect attenuated T switch

A circuit technique for designing a high speed sample-and-hold circuit is proposed. A substrate-biasing-effect attenuated T switch is used during the hold mode of sample-and-hold circuit, the T type structure makes the input-dependent signal feed-through effect neglectable, and a high linearity performance can be assured. Based on SMIC 0.13 μm Standard CMOS process, a sample-and-hold circuit applicable to 12bit, 100 MHz Pipelined ADC is designed. Spectre simulation results show that the using this technique can improve the dynamic performance and the signal-to-noise and distortion ratio (SNADR) and spurs free dynamic range (SFDR) of the sample-and-hold circuit is 85.5 and 92.87 dB, respectively, under the Nyquist input frequency .