| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 547746 | Microelectronics Journal | 2010 | 6 Pages |
Abstract
3D capacitor design parameters have been evaluated in order to improve the capacitance per unit die area. The geometrical issues as well as the process manufacturing issues are both investigated. The main manufacturing issues have been experimentally tested: etching, deposition and warpage of the wafer. An improvement has been observed for the robustness of 3D structures and the density of the capacitor has been increased for several proposed 3D pattern. All capacitors tested in this paper are realised with PICS technology.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
M. Nongaillard, F. Lallemand, B. Allard,