Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
547838 | Microelectronics Journal | 2009 | 6 Pages |
Abstract
The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25 μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8 V and a high trigger current of greater than 120 mA. The robustness has measured to HBM 8 kV (HBM: human body model) and MM 400 V (MM: machine model). The proposed device has a high-level It2 of 52 mA/μm approximately.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Yongseo Koo, Kwangyeob Lee, Kuidong Kim, Jongki Kwon,