Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
547868 | Microelectronics Journal | 2009 | 5 Pages |
Abstract
Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Keivan Navi, Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Omid Hashemipour, Babak Mazloom Nezhad,