Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
548223 | Microelectronics Reliability | 2012 | 5 Pages |
In this work, the two-dimensional numerical simulations of N-type CdSe polycrystalline (poly-) TFTs’ electrical characteristics are performed using a physically based device simulator Atlas/Silvaco. The analytical expressions of trap density models for acceptor- and donor-like traps are defined for poly-CdSe thin film material. The parameters of trap density distributions are extracted based on fitting the simulated and measured results of fabricated CdSe poly-TFTs. It is shown that the discrete numerical method used for trapped charge evaluation in Atlas gives excellent agreement between simulated and measured characteristics, while the continuous numerical approach is less accurate. In addition, the interface trapped charge causing hysteresis in device transfer characteristics is estimated from simulations and shown to increase almost exponentially with the increase of density of shallow tail states.