Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages

In this paper we study board-level thermomechanical reliability of a wafer-level chip-scale package subjected to an accelerated thermal cycling test condition. Different control factors are considered for a robust design towards enhancement of the thermal fatigue resistance of solder joints. These factors include diameter, pitch, and standoff of the solder joints, size of the solder connection opening on the die side, thickness of the pad on the test board, thickness of the test board, and dimension of the die. The Taguchi method along with the technique of analysis of variance are applied in the robust design process. Importance of these factors on the thermomechanical reliability of the package is ranked and the resulting robust design is further verified.