| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 548596 | Microelectronics Reliability | 2006 | 5 Pages |
Abstract
In this paper, the failure process of LDMOS is analyzed. It is found that three peak electric fields locate in the Si/SiO2 interface of LDMOS, which result in three hot spots. From the time the device turns on, the first peak electric field increases and the second one remains constant while the third one decreases. The device fails due to the hot spots induced by the first and the second peak electric fields. Power capability can be enhanced by reducing these two peak electric fields. Methods to improve the power capability are proposed.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Zhilin Sun, Weifeng Sun, Yangbo Yi, Longxing Shi,