Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
548861 | Microelectronics Reliability | 2016 | 11 Pages |
Abstract
In this paper we review and assess the main methods reported to extract the parasitic resistance in staggered amorphous TFTs. We present and discuss examples of their application to bottom gate top contacts a-Si TFTs and AOSTFTs, as well as top gate bottom contacts OTFTs. We show that for modeling purposes, the parasitic series resistance can be considered a second order parameter, as far as its value is much lower than the value of the channel resistance. As a result, we also concluded that for modeling purposes it is not necessary to account for the bias dependence of the parasitic resistance.
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Authors
Antonio Cerdeira, Magali Estrada, Lluis F. Marsal, Josep Pallares, Benjamín Iñiguez,