| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 549017 | Microelectronics Reliability | 2013 | 6 Pages |
Abstract
A framework is proposed to analyze the impact of negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory, embedded within a system running a variety of standard benchmarks. We study DC noise margins in conventional 6T SRAM cells as a function of NBTI/PBTI degradation and provide insights on memory reliability under realistic use conditions.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Chang-Chih Chen, Fahad Ahmed, Linda Milor,