Efficient multi-level modeling technique for determining effective board drop reliability of PCB assembly

In this paper, we develop a new and computationally efficient multi-level approach to investigate board level drop reliability of printed circuit board (PCB) assembly. The approach is composed of two levels of finite element (FE) simulations: solder joint level and board level. Initially, static simulations of the solder joint level were used to obtain the homogenized property of the solder-underfill interconnection. This was followed by explicit FE simulations of the board assembly. The results of the proposed multi-level approach were compared with commonly adopted FE analysis and good correspondence is revealed between the two. Through drop test simulations that involved fifteen Integrated Circuit (IC) packages, as per the standard JESD22-B111 of Joint Electron Device Engineering Council (JEDEC), the critical board locations and interconnection in each location were identified and analyzed. The results reveal that peak stresses occur at the corner of the central package. They also show that the interconnection stresses result mainly from the dynamic bending of the PCB.