Device simulation studies on latch-up effects in CMOS inverters induced by microwave pulse

This paper presents the simulated results of latch-up induced by microwave pulse with respect to pulse parameters, bias voltages and pulse injection conditions. A semi-empirical theoretical model based on the simulated results to access the pulse width and frequency effects on inducing latch-up quantitatively was proposed and agreed with the experimental results reported in the literature. Simulated results also indicated that pulse repetition frequency (PRF) must be far greater than the reciprocal of the minority carrier lifetime to lower the power threshold causing latch-up. Furthermore, excess carrier effects were believed to the primary reason of latch-up and be attributed to the difference between microwave pulse injection conditions.

► Latch-up mechanism due to microwave pulse was investigated using device simulation. ► A semi-empirical model to assess the pulse width and frequency effect was devised. ► Pulse repetition frequency effects on latch-up were investigated. ► Latch-up due to microwave pulse concerning bias voltage scaling down was studied. ► The difference between microwave pulse injection conditions was investigated.