The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices

In this paper we propose a modified model of logical effort for designing optimized buffers in multi-fingered layout scenario in the presence of process induced mechanical stress. It is observed that mechanical stresses induced by tensile and compressive Etch Stop Liner (t-ESL and c-ESL), embedded SiGe (eSiGe) and Shallow Trench Isolation (STI) are not uniform in all the fingers sharing an active region. As a result there is an unaccounted change in the drive current with the number of fingers; thereby causing an unaccounted change in the performance of logic gates implemented using multi-fingered layouts. We explore the impact of mechanical stress induced variability in inverters with multi-fingered devices and derive relationship between the logical effort (LE) and number of fingers (NFs). We use this relationship for predicting CMOS buffer delays more accurately and thus reducing the need for post-layout resizing of their transistors.