Impact of gate placement on RF power degradation in GaN high electron mobility transistors

We have investigated the RF power degradation of GaN high electron mobility transistors (HEMTs) with different gate placement in the source–drain gap. We found that devices with a centered gate show different degradation behavior from those with the gate placed closer to the source. In particular, centered gate devices degraded through a mechanism that has a similar signature as that responsible for high-voltage DC degradation in the OFF state and is likely driven by electric field. In contrast, offset gate devices under RF power stress showed a large increase in source resistance, which is not regularly observed in DC stress experiments. High-power pulsed stress tests suggest that the combination of high voltage and high current stress maybe the cause of RF power degradation in these offset-gate devices.

► We examined the impact of gate placement on RF reliability in GaN HEMTs. ► Devices with a centered gate were found to degrade in a similar way as in DC stress. ► Offset gate devices showed a high increase in source resistance. ► These contrary behaviors were reproduced through pulsed stress.