Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
549407 | Microelectronics Reliability | 2011 | 10 Pages |
Abstract
In power electronic packages, one of the main limiting factors for the module reliability stems from failure of the electrical interconnection which ensures the contact between the chip and the lead frame. The aim of this work is to model, using FEM and some analytical developments, the interconnection heel crack mechanism appearing in service. The forming process impact is particularly evaluated and it is established that the initial residual stresses contribute to limit the wire/ribbon life time.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Y. Celnikier, L. Benabou, L. Dupont, G. Coquery,