| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 549570 | Microelectronics Reliability | 2009 | 5 Pages |
Abstract
We define rules to reduce the ESD test complexity for chips with large pin count. These rules exploit the structural similarity in the pad-ring and have a long history of use without bad experiences. Using these rules an automated software tool can be developed for reduced ESD test generation.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Dejan Maksimovic, Fabrice Blanc, Guido Notermans, Theo Smedes, Thomas Keller,