Thermal conduction analysis and characterization of solder bumps in flip chip package

Flip chip has been widely used in microelectronic packaging to meet the requirements of high density and optimal performance. With the shrinking of the package size, the heat dissipation problem is getting more serious, and the thermal modeling and measurement of flip chip have become hot topics. This paper investigated the thermal performance of the solder bumps using analytical and numerical methods. A lumped thermal resistance network was derived from the mathematical model of heat transfer in the flip chip structure. Common defects were introduced in the 3D finite element model. The impact of the defects on the heat conduction was investigated by the temperature distribution. The thermal performance of the solder bumps was characterized by using the thermal resistances. The relationship between the thermal resistance and the defects size was also studied, and the finite element model describes well the experimental data available from the literature. The results demonstrate that this model is effective for the thermal characterization of solder bumps, and can provide guidelines for failure detection in flip chip package.

► We studied the heat conduction in flip chip using analytical and numerical methods. ► A thermal resistance network was derived from the analytical heat transfer model. ► A 3D FE model was initially constructed to predict the temperature distribution. ► Thermal performance of the solder bumps were characterized using thermal resistance. ► The validated results provide a basis for failure detection in flip chip package.