A variation tolerant current mode low swing signaling approach for gigascale on-chip interface circuit

Enhanced functionality per unit area is the gradually increasing demand of current manufacturing market and that desire has been fulfilled by aggressive down scaling of technology, which has adversely influenced the delay of global interconnect thereby affecting the performance of high speed design. As the time needed to charge or discharge the output node of a circuit is directly proportional to the peak-to-peak swing of the driven signal, there remains an inherent speed advantage in low swing signaling, which is considered to be one of the most suitable options to eliminate signal integrity issues in multi-gbps chip-to-chip communication. This article unveils a detailed report on the shortcomings of existing low swing signaling schemes, where no work is witnessed to generate a certain low voltage swing across any reference voltage ranging from 'Logic 0' to 'Logic 1' of the input signal. To address the same, we have come up with a novel methodology consisting of two different current sources (one at driver and the other at receiver) made of NMOS. In this case, the said reference voltage corresponds to the threshold of the receiver chip, which has to be identified at first. The simulation of proposed low swing signaling scheme is carried out using 65 nm, 45 nm and 22 nm CMOS technology to examine the performance metrics at 1.1 V supply while switching at 2 GHz. This approach does provide extensive delay and energy or PDP savings to outsmart the existing works.