Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6885945 | Microprocessors and Microsystems | 2018 | 9 Pages |
Abstract
Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, the functional yield of CMOS logic gates and minimize the leakage energy per cycle in the subthreshold region. In this work, the PMOS/NMOS strength ratio was balanced using a poly-biasing technique in conjunction with back-gate biasing provided in a 28Â nm fully depleted silicon on insulator (FDSOI) CMOS technology. A 32-bit adder based on minority-3 (min-3) gates and a 16-bit adder based on Boolean gates have been implemented. Chip measurement results of nine samples show highly energy efficient adders. The 32-bit and 16-bit adders achieved mean minimum energy points (MEP) of 20.8Â fJ at 300Â mV and 12.34Â fJ at 250Â mV, respectively. In comparison to adders reported in other works in the same technology, the energy per 1-bit addition of the 32-bit adder is improved by 37%. This improvement in energy consumption is 25% for the 16-bit adder. According to the measurement results of ten chips, the designed adders exhibited functionality down to supply voltages of 110Â mV-125Â mV, without body biasing. Additionally, the minimum Vdd of all the 32-bit adders based on minority-3 gates decreased to 80Â mV by applying a reverse back bias voltage to the PMOS devices. One sample was functional at 79Â mV with a 430Â mV reverse back bias voltage applied to its PMOS devices.
Related Topics
Physical Sciences and Engineering
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Computer Networks and Communications
Authors
Ali Asghar Vatanjou, Even LÃ¥te, Trond Ytterdal, Snorre Aunet,