Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6941986 | Displays | 2018 | 7 Pages |
Abstract
This paper proposes a new gate driver circuit using depletion mode a-IGZO TFTs. The proposed gate driver circuit can prevent Q node, the gate node of pull-up TFT, from discharging during the output pulse duration. For that purpose, our circuit applies sufficient negative gate-to-source bias (Vgs) to the switch TFTs connected to the Q node during that time. Consequently, the leakage current through them is suppressed even though they have a negative threshold voltage (Vth). The proposed circuit has eleven transistors and two capacitors and it requires only two clock signals, which enables us to adopt the circuit at minimum extra cost. It works properly even when Vth is as low as â7.1â¯V. The normalized power consumption of the proposed circuit is also lowered compared with the previously reported circuits when the transistor has negative Vth. The power consumption of the proposed circuit for Vth of â5â¯V increases only nine times that for Vth of 3â¯V.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Jin-Ho Kim, Jongsu Oh, KeeChan Park, Yong-Sang Kim,