High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic

This paper presents a high-speed, energy efficient carry select adder (CSLA) dominated by carry generation logics. The proposed architecture is composed of three functional stages - a Primary Carry Unit (PCU), an Intermediate Wave Carry Unit (WCU) and a Final Selection Unit (FSU) - that are partitioned with the appropriate bit-width. We synthesized the blocks with random logic use functional blocks for which the input and output consist only of carry functions. The CSLA is partitioned into bit-slice logics to reduce the propagation delay, and we analytically optimized the bit-slice width of the functional blocks. The proposed architecture skips the carry computation in the first stage of each bit-slice block. We used 180 nm CMOS technology to implement the proposed CSLA for various input bit widths. The results show that the proposed CSLA reduces the computational delay by 24%, power consumption by 17% and PDP by 37% compared to conventional implementations.