Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6944838 | Microelectronics Journal | 2018 | 7 Pages |
Abstract
This paper introduces an energy-efficient dynamic voltage scaler (DVS) based on charge- pump and binary-weighted capacitor digital to analog converter (BWC-DAC). Conventional DVS architectures suffer from long settling-time beside the limitation of coarse voltage resolution, so we propose DVS architecture based on BWC-DAC architecture. It takes advantage of DAC's reconfigurable structure to provide an output voltage scaled with high resolution of VIN/2N for input voltage VIN and N configuration bits; and Nano-second transition time. However, DAC inherently suffers from low power efficiency because it requires frequent reset to maintain the output voltage. To overcome this issue, a high efficiency charge-pump is employed to restore the charges in DAC's capacitors without the need to reset which results in improved power efficiency. The proposed DVS with a 6-bit DAC and a feedback controlled circuit have been implemented using a 130â¯nm CMOS process. The measurement results show an accurate 64 voltage levels of the 6-bit DAC from 0â¯V to 1.476â¯V, when supplied by an input voltage of 1.5â¯V. We achieved a peak efficiency of 84% for load current ranging from 1â¯Î¼A-14.76â¯Î¼A. Furthermore, it provides an extremely short settling time that is as short as 83.6 Nano second.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
A.N. Ragheb, HyungWon Kim, Jae-Jin Lee,