A high-speed small-area pixel 16 × 16 ISFET array design using 0.35-μm CMOS process

This paper reports the design of a 16 × 16 ion-sensitive field-effect transistor (ISFET) chip with tightly arranged small pixels that can work in relatively higher speeds. During the chip design, we thoroughly considered the pixel area, speed, power consumption, and extensibility. The chip was fabricated using a conventional 4-metal 0.35-μm CMOS process. As a result, we obtained a chip's pixel area of 7.4 μm × 7.4 μm, power consumption of 3.3 V × 4 mA, and scanning rate reaching 6.25 M pixels/s. The passivation layer, mainly consisting of Si3N4, was directly treated as the sensing film. By arranging the overall layout tightly, this chip could be regarded as a module to expand the scale of ISFET arrays and can be used in applications having larger scale arrays. Initially, we obtained an average sensitivity of 20 mV/pH ±2 mV/pH and modified it up to 35 mV/pH ±2 mV/pH by rinsing it in BOE (Buffered Oxide Etch) with a volumn ratio of 1:4:4 (HF:H2O:NH4F) for 15 min.