Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6944879 | Microelectronics Journal | 2018 | 6 Pages |
Abstract
A statically triggered 3â¯Ãâ¯VDD-tolerant electrostatic discharge (ESD)detection circuit using only low-voltage devices in a 90-nm 1.2-V CMOS process is proposed. A bias circuit is added to enhance the ESD trigger efficiency. Since no NMOSFETs are used, it is unnecessary to use any deep N-well even though the circuit can sustain 3â¯Ãâ¯VDD stress. The proposed detection circuit can generate a 38â¯mA current to turn on the substrate-triggered silicon controlled rectifier (SCR) during ESD events. Under normal operating conditions, all the devices are free from over-stress voltage. Without the gate leakage current of a MOS capacitor, the leakage current is only 63â¯nA under 3â¯Ãâ¯VDD stress at 25â¯Â°C. The simulation result shows the proposed circuit can be successfully used for a 3â¯Ãâ¯VDD-tolerant I/O buffer.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Zhaonian Yang, Yuan Yang, Ningmei Yu, Juin J. Liou,