Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6944919 | Microelectronics Journal | 2018 | 6 Pages |
Abstract
In this paper, two leakage-combating analog switches for low-speed sample-and-hold (S/H) circuits are proposed. In conventional low-leakage switch, the potential drop along MOSFET is clamped to zero to suppress sub-threshold leakage. Based on this switch, the proposed leakage-combating analog switches can suppress p-n junction reverse-biased leakage by clamping the potential drop along parasitic p-n junction to zero. The proposed two switches are designed and fabricated with a 0.13â¯Î¼m CMOS process in a prototype chip. The experiment results illustrate that the order of magnitude of the leakages from the proposed two switches only change from 10â15â¯A to 10â12â¯A in the temperature range from â20â¯Â°C to 120â¯Â°C, which is many times lower than that of the traditional switch. FFT simulations of the S/H circuits using the proposed switches are performed. On the condition of 0.01â¯kS/s and 100â¯Â°C, the THDs of the S/H circuits with these proposed switches are â53.98â¯dB, â61.09â¯dB respectively. The proposed switches are suitably applied in low-speed S/H circuits.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Jiangtao Xu, Xiaolin Shi, Zhiyuan Gao, Kaiming Nie,