Modeling of SOI four-gate transistor (G4FET) using multidimensional spline interpolation method

A numerical multidimensional spline interpolation method for CAD implementation of silicon-on-insulator (SOI) four-gate transistors (G4FET) is presented in this paper. The model is generated using available data for wide range of biasing and geometric variation and an independent set of test data is then used to validate its predictive accuracy. The objective of this DC model is to determine the drain current as a function of multiple terminal voltages and device geometry. The method is shown to work very well when independent variables do not exceed the range of training data set used for the model development. Both n-channel and p-channel G4FET models have been developed and validated using TCAD and experimental data. Moreover, models of both devices have been implemented in circuit simulator for simulating experimentally demonstrated innovative G4FET circuit.