A novel compact analog counter for high density SPAD array imagers

This paper introduces a compact analog counter for high-density single photon avalanche diode (SPAD) array imagers. We propose an innovative charge transfer approach based on pulse edge triggering that can significantly reduce the amount of transferred charge, leading to a great improvement on the dynamic counting range without sacrificing the pixel area. Designed by standard 0.18 μm CMOS technology, the analog counter features a 9-bit counting resolution with the reduced occupation area of 230 μm2. Post-layout simulation reveals that for the 9-bit analog counter, the differential nonlinearity (DNL) and integral nonlinearity (INL) are within the ±0.35 LSB and ±1 LSB ranges, respectively and the nonuniformity is as low as 1.81%, validating the high precision of photon counting. Thanks to the compactness and the high performance, the novel analog counter is suitable for the high-density integration of the SPAD array imagers.