High speed and low cost synchronous counter design in quantum-dot cellular automata

Quantum-dot Cellular Automata (QCA) is a very interesting nano-scale technology. Extremely small feature size and ultra-low power consumption are the most important features of QCA compared to CMOS. Counters are considered as one of the most fundamental components in sequential circuits. Previous QCA synchronous counters (QSCs) have been designed and simulated using two methods. In the first method, QSCs utilize direct mapping flip-flop designs in CMOS technology to QCA. In the second method, QSCs are designed with the inherent capability of QCA technology. Despite being attractive, mentioned approaches have constraints (i.e. long wire length and area issues). In this brief, design and simulation of a QSC are presented through combining the two approaches. Experimental results reveal that the novel combination not only overcomes limitations of the above methods, but also improves delay and cost function (at least two times lower than the best previous QSCs).