Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6945074 | Microelectronics Journal | 2018 | 8 Pages |
Abstract
A digital-domain foreground calibration method simultaneously correcting mismatch errors in main capacitive digital to analog converter (CDAC) and “segment error” between main CDAC and sub-CDAC of split-CDAC array in high resolution successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The actual weight is obtained with the digital-domain weight estimation algorithm. This proposed digital-domain calibration saves silicon area by eliminating the need for a dedicated calibration DAC employed in conventional CDAC mismatch calibration schemes. Behavioral simulation shows the proposed calibration is capable of correcting mismatch errors and “segment error” of split-CDAC array, and improving SNDR from 67.3â¯dB to 92.8â¯dB in a prototype 16 bit split-CDAC SAR ADC.
Keywords
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Rui Guan, Jing Jin, Jianjun Zhou,