Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6945086 | Microelectronics Journal | 2018 | 8 Pages |
Abstract
This paper proposes an integrated envelope tracking CMOS power amplifier for LTE application. It is shown in the paper that a common-drain power amplifier has improved linearity performance and less switching-ripple leakage of the supply voltage, as compared to its common-source counterpart. Hence, the proposed envelope tracking power amplifier is designed with a common-drain structure and post-simulated in a 0.18 μm CMOS process. By utilizing the common-drain structure, the supply modulator can be implemented using a switching-only regulator, and neither a linear regulator nor a hybrid technique is required. For a signal at 1.85 GHz with a 5-MHz bandwidth and 6.5 dB PAPR, the CMOS envelope tracking power amplifier achieves a power added efficiency of 30% and an Adjacent Channel Leakage Power Ratio (ACLR) of â32 dBc at an average output power of 22 dBm. By employing envelope tracking technique, the power added efficiency is improved by up to 5 dB, as compared to that of the stand-alone power amplifier.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Mohammad Javad Zavarei, Mohammad Taherzadeh-Sani,