Design and optimization of the ring oscillator based injection locked frequency dividers

In this paper, the large signal operation of the ring oscillator based injection locked frequency divider is analyzed considering the trade-offs among the operating frequency, locking range and power consumption. A large signal model is used to reveal several key findings such as voltage-limited locking ranges and asymmetry between the upper and lower locking bands. They are applied to the optimize the dividers maintaining a good balance among design considerations. Several prototypes, including the divide-by-2 with 3 and 5 stages of inverters, divide-by-3 and divide-by-5, are implemented in a standard 0.18 µm CMOS technology to verify the operation under a large injected signal. As an extension, dual-modulus prescalers are further designed by the integration of switches for different ways of signal mixing. Measurements results show the proposed divide-by-2/3 unit and a divide-by-8/9 with this unit are able to work up to 8 GHz and 4.0 GHz with maximum power consumption of 0.7 mW and 1.5 mW respectively.