System level fault-tolerance core mapping and FPGA-based verification of NoC

This paper proposes a fault-tolerance network on chip (FTNoC) algorithm that incorporates a core graph unit, which is responsible for mapping and scheduling the core graph on the NoC architecture. Fault tolerance unit collects all the fault information from the mapped NoC platform and provides various solutions for different types of fault. This results in reliable core mapping and improved performance when a fault-related error occurs on an NoC. The proposed FTNoC algorithm was simulated and verified on Kintex-7 (KC705) FPGA board. The results revealed a reduction in area, power consumption and performance improvement compared with previous state-of-the art works.