Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6945344 | Microelectronics Journal | 2016 | 8 Pages |
Abstract
This paper presents a high gain CMOS transimpedance amplifier (TIA) design using staggering technique to obtain high bandwidth and low gain ripple. To provide the staggered frequency response, the proposed TIA employs a Ï-network as a transimpedance stage along with a novel Folded Cascade-based shunt amplifier as a post amplifier stage. Simulation of the proposed TIA for 1.8 V 0.18 μm CMOS technology shows that a gain of 58 dB Ω with 1 dB Ω gain-ripple over a bandwidth of 8.1 GHz can be achieved while the whole TIA circuit consumes 38.2 mW from 1.8 V power supply. The simulated average input noise current spectral density is about 15pA/Hz within the TIA frequency band.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Majid Rakide, Mahmood Seifouri, Parviz Amiri,