Ternary cyclic redundancy check by a new hardware-friendly ternary operator

This paper presents a new ternary operator for cyclic redundancy check in ternary logic with high hardware efficiency. It shows the essential properties of a ternary operator for calculating CRC. Gate-level implementation of CRC-16 is exemplified and comprehensively explained in this paper. Transistor-level realizations of the new and the previous operators are also given in full detail. This paper demonstrates that the employment of the proposed operator reduces hardware components such as the elimination of one entire operator in both transmitter and receiver sides in comparison with ternary SUM. In addition, simulation results by HSPICE and 32 nm CNTFET technology shows about 20.6% energy reduction for one of the implementation methods of the proposed operator with respect to the previously presented one (CCW CYCLE). Furthermore, five fewer transistors are needed to design the proposed operator in contrast with both operators SUM and CCW.