Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6945373 | Microelectronics Journal | 2016 | 12 Pages |
Abstract
The data bus is a major component of high power consumption in small process high-performance systems and in systems-on-chip (SoC) design. This paper presents an analysis of different state-of-the-art techniques for reducing the power of off-chip memory bus interface, with proposing an approach overcoming some limitations existing in the state-of-art methods. More precisely, the paper introduces a serialization (S) method combined with cache-based encoding scheme, aiming at saving the optimal possible power for off-chip memory bus. Bus serialization reduces the number of transmission wires, while a Serialization-Widening (SW) approach reduces the bus capacitance and the number of transmission wires. Experimental results show that, for off-chip data bus, the serialization approach with cache-based encoding achieves 31% and 52% power reduction for single-core and multi-core applications, respectively, when using fixed voltage and frequency with 128 bits data bus.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Khader Mohammad, Ahsan Kabeer, Tarek M. Taha, Muhsen Owaida, Mahdi Washha,