| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6945376 | Microelectronics Journal | 2016 | 16 Pages |
Abstract
The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuits.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Tripurari Sharan, Vijaya Bhadauria,