Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6945562 | Microelectronics Reliability | 2018 | 7 Pages |
Abstract
In the output stage of power ICs, large array devices (LAD) of MOSFETs are usually used to drive a considerable amount of current. Electrostatic discharge (ESD) self-protection capability of LAD is also required. ESD layout rules are usually adopted in low voltage CMOS transistors to improve the ESD performance but with a large layout area. In this paper, a modified RC gate-driven circuit with gate signal control circuit is developed to keep the minimum device layout rule while achieving ESD self-protection. Thus, it results in a very small layout area increment while keeps the LAD operates safely in normal operation and gains good ESD protection level.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Shao-Chang Huang, Hung-Wei Chen, Jen-Hang Yang, Mi-Chang Chang,