Study of the operation and SET robustness of a CMOS pulse stretching circuit

This paper analyzes the normal response and the sensitivity to Single Event Transients (SETs) of a CMOS pulse stretching circuit used for the SET pulse width measurement. The pulse stretcher based on two cascaded asymmetrically sized inverters, designed in IHP's 130 and 250 nm bulk CMOS technologies, has been studied. Results from SPICE simulations have confirmed that both the normal response (pulse stretching) and the SET robustness (critical charge) of the pulse stretcher are dominantly influenced by the PMOS-to-NMOS sizing ratio. In addition, the operation and SET robustness of the pulse stretcher are influenced by the load, operating temperature, supply voltage variations, process corners and parasitic capacitances of interconnections. The typical process-induced mismatch in transistors' sizes is not a critical issue in this case. It was demonstrated that the multi-stage pulse stretching configuration is more suitable for obtaining wider pulses, but on the other hand is more susceptible to SETs than the single-stage (two-inverter) pulse stretcher. Based on the acquired results, a general approach for the design of a CMOS pulse stretcher, taking into consideration the impact of all analyzed parameters on its normal response and SET robustness, has been proposed.