Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6946407 | Microelectronics Reliability | 2016 | 8 Pages |
Abstract
The results of this investigation indicate that: (i) the analyzed devices have a breakdown voltage (measured at 1Â mA/mm) higher than 600Â V; in off-state, drain current originates from gate-drain leakage for drain voltages (VDS) smaller than 500Â V, and from vertical leakage through the conductive substrate for higher drain bias. (ii) step-stress experiments carried out in off-state conditions may induce instabilities in both drain-source conduction and gate leakage. Failure consists in the shortening of the gate junction, and occurs at VDS higher than 600Â V. (iii) in forward bias, the p-type gate is stable up to 7Â V; for higher gate voltages, a time-dependent degradation is detected, due to the high electric field across the AlGaN barrier; (iv) TIM analysis performed under short-circuited load conditions revealed hot spots at the drain side of the channel in the access region, thus indicating that these regions may behave as weak spots under high bias operation. Cumulative device degradation under such repeating pulses has also been revealed. (v) TLP tests were carried out to evaluate the voltage limits of the devices under off-state and on-state conditions. The results described within this paper provide relevant information on the reliability issues of state-of-the-art normally-off HEMTs with p-type gate.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
M. Meneghini, O. Hilt, C. Fleury, R. Silvestri, M. Capriotti, G. Strasser, D. Pogany, E. Bahat-Treidel, F. Brunner, A. Knauer, J. Würfl, I. Rossetto, E. Zanoni, G. Meneghesso, S. Dalcanale,