Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6946582 | Microelectronics Reliability | 2015 | 6 Pages |
Abstract
The formation of conductive percolation path in high-κ (HK)/interfacial layer (IL) dielectric stack is accompanied by dynamic changes in the electrical and chemical properties at the nanometer length scale. It is therefore essential to study these breakdown (BD) events using high-precision nanoscale characterization tools to investigate the physical mechanisms of failure for advanced HK dielectric based devices. In this work, we carry out a new method for electrical nanoprobing of HfO2/SiOx (x< 2) dielectric stacks for failure using a combined UHV-scanning electron microscopy/scanning tunneling microscopy (SEM/STM) system to locally stress HfO2/SiOx stacks, followed by focussed ion-beam (FIB) sample preparation of these isolated failed devices and physical analysis of the BD sites using transmission electron microscopy (TEM). Our results confirm the multiple physical phenomena associated with localized BD, such as dielectric-breakdown-induced epitaxy, percolation of the dielectric layers, gate electrode material migration and melting of the Si substrate at the BD region of HfO2/SiOx dielectric stacks. Our method of nanoprobing and correlated TEM analysis would be very useful in better localizing the BD defects for TEM studies thereby enhancing the success rate for failure defect detection and enabling better reliability study of the advanced nanoscale devices.
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Authors
K. Shubhakar, M. Bosman, O.A. Neucheva, Y.C. Loke, N. Raghavan, R. Thamankar, A. Ranjan, S.J. O'Shea, K.L. Pey,