Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6946594 | Microelectronics Reliability | 2015 | 5 Pages |
Abstract
The ESD robustness of multi-finger nMOSFET transistors in an advanced RF CMOS technology has been analysed by both TLP and, for the first time, by transient interferometric mapping (TIM) technique. Failure current It2 has been studied for different source, gate and bulk contact grounding configurations, for TLP pulse duration between 25Â ns and 550Â ns and TLP rise time of 1Â ns and 10Â ns. The lateral distribution of dissipated thermal energy during a TLP pulse has been measured by TIM. The ESD failures for selected pad configurations are investigated by DC-IV and physical failure analysis. The highest (lowest) It2 has been revealed for floating (grounded) gate and bulk pads, and attributed to the pn junction (gate oxide) damage.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Matteo Rigato, Clément Fleury, Michael Heer, Mattia Capriotti, Werner Simbürger, Dionyz Pogany,